Power management is necessary to reduce standby power consumption of low-power portable applications such as mobile phones and personal digital assistants (PDAs). A low-dropout regulator (LDO) is a type of voltage regulator that is widely utilized in power management integrated circuits. They are especially suitable for applications that require a low-noise and precision supply voltage with minimum off-chip components. With the rapid development of system-on-chip designs, there is a growing trend towards power-management integration. On-chip and local LDOs are used to power up system sub-blocks individually and this can significantly reduce cross talk, improve voltage regulation and eliminate voltage spikes. However, an off-chip capacitor, which provides LDO stability and good load transient response, cannot be eliminated in conventional LDO designs based on pole-zero cancellation. This is the main obstacle to the full integration of LDOs in system-on-chip designs. Though there are some LDO designs with internal compensation, the frequency and transient performances are sacrificed as tradeoffs.